1. Field of the Invention
The present invention relates to a generation method of generating the data of the patterns of a plurality of masks used in at least one of a plurality of exposure apparatuses, a storage medium, and an information processing apparatus.
2. Description of the Related Art
An exposure apparatus is used in a lithography process that is a semiconductor device manufacturing process. In the lithography process, the circuit pattern of a semiconductor device is transferred to a substrate (for example, silicon substrate, glass substrate, or wafer). The exposure apparatus includes an illumination optical system that illuminates a mask (reticle) with light from a light source, and a projection optical system that projects the pattern (circuit pattern) formed on the mask to the substrate.
To cope with the recent finer design rules of semiconductor devices, the exposure apparatus performs multiple patterning (multiple exposure) in which a substrate is exposed a plurality of times using a plurality of masks, and the patterns of the plurality of masks are overlaid and formed in one layer on the substrate. The resolution limit at which the exposure apparatus cannot obtain a sufficient exposure margin is generally represented by hp=k1×λ/NA where hp is the half of the shortest distance between adjacent patterns, that is, the half pitch, k1 is the process factor, λ is the wavelength of exposure light (exposure wavelength), and NA is the numerical aperture of the projection optical system. The multiple patterning is a technique of dividing a pattern having a half pitch smaller than that corresponding to the resolution limit of the exposure apparatus into a plurality of patterns (that is, a plurality of masks) and exposing the masks, thereby resolving the pattern smaller than the resolution limit in one exposure.
As a technique associated with multiple patterning, for example, U.S. 2011/0078638 proposes a method of dividing a mask pattern (pattern (target pattern) to be transferred to a substrate) into a plurality of patterns. U.S. 2011/0078638 discloses a method of dividing a pattern using a conflict graph and mathematical programming. The conflict graph is formed form nodes and edges. When dividing a pattern, each pattern element that constitutes the pattern is represented by a node, and pattern elements having a distance exceeding the resolution limit are connected by an edge. In U.S. 2011/0078638, a pattern is divided using mathematical programming such that an edge has different mask numbers at its two ends. U.S. 2011/0078638 also discloses a method of reducing (solving) division contradictions (the number of nodes or edges of a conflict graph) from the design point of view by dividing one pattern element into a plurality of pattern elements.
U.S. 2007/0031738 proposes another method of reducing division contradictions from the design point of view. U.S. 2007/0031738 discloses a method of reducing division contradictions from the design point of view by grouping a plurality of pattern elements spaced apart by a predetermined distance or more.
On the other hand, for low k1 lithography, it becomes difficult to faithfully transfer a predetermined pattern of a two-dimensional layout (a pattern spreading in the vertical and horizontal directions) to a substrate. Recently, a circuit pattern forming method called a one-dimensional layout technology is proposed in “Michael C. Smayling et. al., “Low k1 Logic Design using Gridded Design Rules” Proc. of SPIE Vol. 6925 (2008)”. In this technology, a single-pitch L/S (line and space) pattern is formed. Then, pattern elements such as hole patterns and cut patterns are formed on an iso-grid at a plurality of positions in the same image dimensions. The single-pitch L/S pattern is cut by the pattern elements, thus forming a circuit pattern. The one-dimensional layout technology can not only reduce the exposure area as compared to the two-dimensional layout technology but also technically facilitate the exposure itself.
In the techniques disclosed in U.S. 2011/0078638 and U.S. 2007/0031738, however, a pattern is divided or division contradictions from the design point of view are reduced assuming a pattern of a two-dimensional layout. Hence, the method of reducing the division contradictions from the design point of view by dividing a pattern element into a plurality of pattern elements cannot be applied to the one-dimensional layout where one pattern element is not divided.
U.S. 2007/0031738 proposes discloses a method of grouping noncritical pattern elements spaced apart by a predetermined distance (critical pitch) or more. However, a method of grouping critical pattern elements is not disclosed in U.S. 2007/0031738, and many division contradictions from the design point of view remain unsolved.